1. Field of the Invention
The present invention relates generally to synchronous semiconductor memory devices and in particular to synchronous semiconductor memory devices synchronized with a clock signal to allow data of a predetermined number of bits to be read/written from/to the same.
2. Description of the Background Art
Conventionally, as a semiconductor device using a memory cell which stores information by means of the electric charge held in a capacitor, a specification referred to as a synchronous dynamic random access memory (referred to as an SDRAM hereinafter) has been standardized and widely used as a computer's memory device and the like.
FIG. 11 is a block diagram showing a schematic configuration of a conventional SDRAM. In FIG. 11 the SDRAM includes a clock buffer 151, a control signal buffer 152, an address buffer 153, a mode register 154, a control circuit 155, four memory arrays 156-159 (banks #0-#3), and an I/O buffer 160.
Clock buffer 15 is activated in response to an external control signal CKE to transmit an external clock signal CLK to control signal buffer 152, address buffer 153 and control circuit 155. Control signal buffer 152 is synchronized with external clock signal CLK from clock buffer 151 to latch and feed external control signals /CS, /RAS, /CAS, /WE, DQM to control circuit 155. Address buffer 153 is synchronized with external clock signal CLK from clock buffer 151 to latch and feed external address signals A0-Am, wherein m represents an integer no less than zero, and bank select signals BA0, BA1 to control circuit 155.
Mode register 154 stores a mode designated by external address signals A0-Am and other signals and outputs an internal command signal corresponding to the stored mode. Memory arrays 156-159 each have a plurality of memory cells arranged in rows and columns and each storing 1-bit data. The plurality of memory cells are previously divided into groups each having n+1 memory cells, wherein n represents an integer no less than zero.
Control circuit 155 responds to signals from clock buffer 151, control signal buffer 152, address buffer 153 and mode register 154 by producing various internal signals to generally control the SDRAM. Control circuit 155 in write and read operations responds to bank select signals BA0, BA1 by selecting any of four memory arrays 156-159 and to address signals A0-Am by selecting n+1 memory cells from the selected memory array. The selected n+1 memory cells are activated to be coupled with I/O buffer 160.
I/O buffer 160 in write operation feeds externally input data D0-Dn to the selected n+1 memory cells and in read operation externally outputs data Q0-Qn read from the n+1 memory cells.
FIG. 12 is a circuit block diagram showing a configuration of a portion of the FIG. 11 memory array 156 and a portion associated therewith. In FIG. 12, memory array 156 includes a plurality of memory cells MCs arranged in rows and columns, a word line WL provided for each row of memory cells, a pair of bit lines BL and /BL provided for each column of memory cells. Memory cell MC includes an n channel MOS transistor Q for access, and a capacitor C for information storage.
Each word line WL has one end connected to a row decoder (not shown) included in control circuit 155. The row decoder is responsive to a row address signal produced from address signals A0 to Am for selecting any of the plurality of word lines WLs to set word line WL to a selected level or a high level.
At one end of each pair of bit lines BL and /BL, an equalizer EQ is arranged for equalizing paired bit lines BL and /BL to a bit line potential VBL (=VCC/2) before memory cell MC is selected. Equalizer EQ includes an n channel MOS transistor 161 connected between bit lines BL and /BL, an n channel MOS transistor 162 connected between bit line BL and a node N162, and n channel MOS transistor 163 connected between bit line /BL and node N162. MOS transistors 161-163 have their respective gates receiving a bit line equalization signal BLEQ. Node N162 receives bit line potential VBL.
Between paired bit lines BL and /BL a sense amplifier SA is arranged for amplifying a slight potential difference appearing between bit lines BL and /BL after memory cell MC is selected. Sense amplifier SA includes an n channel MOS transistor 164 connected between bit line BL and a node N164, and n channel MOS transistor 165 connected between bit line /BL and node N164, a p channel MOS transistor 166 connected between bit line BL and a node N166, and a p channel MOS transistor 167 connected between bit line /BL and node N166. MOS transistors 164, 166 have their respective gates both connected to bit line /BL and MOS transistors 165, 167 have their respective gates both connected to bit line BL. Nodes N164 and N166 are connected via n and p channel MOS transistors 168 and 169 to a line for a ground potential GND and a line for a power supply potential VCC, respectively. N and p channel MOS transistors 168 and 169 have their respective gates receiving sense amplifier activation signals S0N and ZS0P, respectively, output from control circuit 155.
Bit lines BL and /BL have their one ends connected via a column select gate CSG to one end of a pair of data input/output lines IO and /IO. Column select gate CSG includes an n channel MOS transistor 171 connected between bit line BL and data input/output line IO, and an n channel MOS transistor 171 connected between one end of bit line /BL and data input/output line /IO. n channel MOS transistors 170, 171 have their respective gates connected to one end of a column select line CSL.
Each column select line CSL has the other end connected to a column decoder (not shown) included in control circuit 155. The column decoder is responsive to a column address signal produced from address signals A0 to Am for selecting any of the plurality of column select lines CSLs to set column select line CSL to a selected level or a high level. The number of the FIG. 12 circuits is equal to that of bits of data that can be simultaneously input/output, i.e., n+1.
FIG. 13 is a time chart representing a data read operation of the SDRAM shown in FIGS. 11 and 12. Assuming that memory array 156 is selected, description will now be made only of a single data input/output terminal. Initially, an active command ACT (/RAS of low level, /CAS of high level, /CS of low level, /WE of high level) and a row address signal are input. In FIG. 12, bit line equalization signal BLEQ goes inactive low, the equalizer's n channel MOS transistors 161-163 turn off, and equalizing paired bit lines BL and /BL is stopped. Simultaneously, row activation signal RAS goes active high and word line WL corresponding to a row address signal is raised selected high. Thus, memory cell MC connected to word line WL has n channel MOS transistor Q turned on and bit lines BL and /BL have a potential slightly varied depending on the amount of charge of capacitor C of activated memory cell MC.
Then, sense amplifier activation signal S0N goes active high and sense amplifier activation signal ZS0P also goes active low and sense amplifier SA is activated. When bit line BL has a potential slightly higher than bit line /BL, MOS transistors 165, 166 have a resistance smaller than MOS transistors 164, 167 so that the bit line BL potential is pulled high and the bit line /BL potential is pulled low. When bit line BL has a potential slightly lower than bit lines /BL, MOS transistors 165, 166 has a resistance larger than MOS transistors 164, 167 so that the bit line BL potential is pulled low and the bit line /BL potential is pulled high.
Then a read command RE (/RAS is high, /CAS is low, /CS is low, /WE is high) and a top column address signal are input. In the initial cycle, column select line CSL1 corresponding to the top column address signal is raised selected high and column select gate CSG associated with the column select line CSL1 has its n channel MOS transistors 170, 171 turned on and the pair of bit lines BL, /BL associated with the column select line CSL1 are coupled with the pair of data input/output lines IO, /IO. The data transmitted on the pair of data input/output lines IO, /IO is externally output via I/O buffer 160. Thereafter, by a burst length (in the figure it is two), following the top column address signal a column address signal is produced internal to the SDRAM and column select line CSL corresponding to the column address signal is selected and data is output from the column. It should be noted that in FIG. 13 a signal COLP goes high during a burst period.
Finally, a precharge command PRE (/RAS is low, /CAS is high, /CS is low, /WE is low) is input. Responsively, row activation signal RAS goes low and word line WL is pulled non-selected low. Thus, memory cell MC connected to word line WL has n channel MOS transistor Q turned off and a potential of bit lines BL, /BL amplified by sense amplifier SA to power supply potential VCC or ground potential GND is held in capacitor C of memory cell MC. Then, bit line equalization signal BLEQ is raised active high and the equalizer's n channel MOS transistors 161-163 turn on and bit lines BL, /BL are equalized to bit line potential VBL. Thus the preparation for the next data read operation completes. As such, in the SDRAM, active command ACT, read command RE and precharge command PRE can be repeatedly applied to read data from memory cells of different rows.
In the SDRAM, a read command RE' with an auto-precharge function is standardized, as shown in FIG. 14, to simplify the procedure of the data read operation thereof. With read command RE', a precharge operation is automatically provided without inputting precharge command PRE when a read operation is complete.
In write operation, as shown in FIG. 12, column select line CSL corresponding to a column address signal is raised selected high and column select gate CSG associated with the column select line CSL conducts and the pair of bit lines BL, /BL is coupled with the pair of data input/output lines IO, /IO. Then, according to read data, via data input/output lines IO, /IO one of bit lines BL, /BL is set high and the other is set low and word line WL corresponding to a row address signal is also raised selected high for a predetermined period of time and bit line BL or IBL has its potential stored in capacitor C of memory cell MC. For a column which is not coupled with the pair of data input/output lines IO, /IO, as in read operation, paired bit lines BL, /BL are stopped from being equalized, word line WL is raised high, sense amplifier SA is activated, word line WL falls low and paired bit lines BL, /BL are equalized, and data is rewritten into memory cell MC.
Furthermore, data may be written using either an active command, a write command and a precharge command, or an active command and a write command with the auto-precharge function.
In a conventional SDRAM, however, when read command RE with the auto-precharge function is input a precharge operation starts at the cycle following that at which a read operation completes. As such if, particularly with a burst length of one applied, read command RE' is input at an earlier timing, then word line WL falls low before sense amplifier SA sufficiently amplifies a potential difference between paired bit lines BL and /BL, as shown in FIG. 15, so that sufficient charge cannot be written into capacitor C of memory cell MC. Thus read command RE' cannot be input early to obtain output data Q1 early. This also applies to inputting a write command with the auto-precharge function.
Therefore, a main object of the present invention is to provide a synchronous semiconductor memory device capable of satisfactorily rewriting data into a memory cell in data read/write operation.
Briefly speaking of the present invention, in response to a predetermined first period of time elapsing following a low select circuit setting a word line to a selected level and in response to a completion of the selecting said bit line pairs via which data are read/written in accordance with the read/write command, a signal generation circuit responsively applies to the row select circuit a reset signal for setting the word line to a non-selected level. As such, by appropriately setting the first period of time, a potential difference of paired bit lines can be sufficiently amplified before a word line is set to the non-selected level, to allow data to be sufficiently rewritten into a memory cell. Furthermore, if data is read earlier, data will not be insufficiently rewritten, so that the data can be read rapidly.
Preferably, the row select circuit is activated in response to an active command being input, a sense amplifier is activated following a second predetermined period of time after the active command is input, the column select circuit is activated in response to a read/write command being input after the active command is input, and the signal generation circuit applies the reset signal to the row select circuit in response to a third predetermined period of time elapsing after the sense amplifier is activated and in response to a completion of the selecting said bit line pairs via which data are read/written in accordance with the read/write command. As such, data can be rewritten into a memory cell further accurately.
Still preferably, there can also be provided an equalizer equalizing each pair of bit lines to a predetermined potential in response to the row select circuit setting a word line to the non-selected level. As such, data can be accurately read from an activated memory cell.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.